Call for Papers (download the pdf file)
The Symposium will be held in Arlington/Washington DC, USA, at the Hilton Arlington & Towers Hotel. The hotel is located in the upscale Ballston area of Arlington, Virginia and is linked by skybridge to the Ballston Common Mall and NSF Office Complex. The Ballston neighborhood provides close proximity to high-tech engineering firms and government research offices
The topics include (but are not limited to) the following ones:
Analysis, Modeling and Enhancement
Defect/Fault analysis and models; statistical yield modeling; critical area and other metrics.
Restructuring and Reconfiguration
Repairable logic, fault-isolation, reconfiguration, and repair; restructurable and reconfigurable circuit design; on-line reconfiguration and repair.
Built-in self-test; delay fault modeling and diagnosis; testing for analog and mixed circuits.
Detection, Correction, and Recovery
Self-testing and self-checking design; error-control coding; fault masking logic design; recovery scheme using space/time redundancy.
- Defect and
Reliable circuit synthesis; radiation hardened/tolerant processes and design; transient/soft faults (SEU) tolerance, delay defect/fault tolerance.
Analysis and Validation
Fault injection techniques and environments; dependability characterization of IC and systems.
Defect and fault tolerance in Carbon Nanotubes, Quantum-dot Cellular Automata, Quantum Computing, and Single Electron Transistors.
Design for defect and fault tolerance in safety critical systems and applications such as: automotive, railway, avionics, industrial control, and space.
12, 2006 (EXTENDED)
Notification of acceptance: July 21, 2006 (EXTENDED)
Camera ready full papers: July 31, 2006
The proceedings will be published by the IEEE Computer Society. Authors will have the opportunity to submit extended versions of the papers published at the symposium in a special issue of a journal. For general information, contact the General co-Chairs. For paper submission information, contact the Program co-Chairs.