Call for Papers (download the pdf file)

DFT is an annual Symposium providing an open forum for presentations in the field of defect and fault tolerance in VLSI systems inclusive of emerging technologies. One of the unique features of this symposium is to combine new academic research with state-of-the-art industrial data, necessary ingredients for significant advances in this field. All aspects of design, manufacturing, test, reliability, and availability that are affected by defects during manufacturing and by faults during system operation are of interest.
The Symposium will be held in Arlington/Washington DC, USA, at the Hilton Arlington & Towers Hotel. The hotel is located in the upscale Ballston area of Arlington, Virginia and is linked by skybridge to the Ballston Common Mall and NSF Office Complex. The Ballston neighborhood provides close proximity to high-tech engineering firms and government research offices
The topics include (but are not limited to) the following ones:
  1. Yield Analysis, Modeling and Enhancement
    Defect/Fault analysis and models; statistical yield modeling; critical area and other metrics.
  2. Repair, Restructuring and Reconfiguration
    Repairable logic, fault-isolation, reconfiguration, and repair; restructurable and reconfigurable circuit design; on-line reconfiguration and repair.
  3. Testing Techniques
    Built-in self-test; delay fault modeling and diagnosis; testing for analog and mixed circuits.
  4. Error Detection, Correction, and Recovery
    Self-testing and self-checking design; error-control coding; fault masking logic design; recovery scheme using space/time redundancy.
  5. Defect and Fault Tolerance
    Reliable circuit synthesis; radiation hardened/tolerant processes and design; transient/soft faults (SEU) tolerance, delay defect/fault tolerance.
  6. Dependability Analysis and Validation
    Fault injection techniques and environments; dependability characterization of IC and systems.
  7. Emerging Technologies
    Defect and fault tolerance in Carbon Nanotubes, Quantum-dot Cellular Automata, Quantum Computing, and Single Electron Transistors.
  8. Safety Critical Systems
    Design for defect and fault tolerance in safety critical systems and applications such as: automotive, railway, avionics, industrial control, and space.
Prospective authors should adhere to the following deadlines:

Submission deadline:                       June 12, 2006   (EXTENDED)
Notification of acceptance:               July 21, 2006    (EXTENDED)
Camera ready full papers:                July 31, 2006

The proceedings will be published by the IEEE Computer Society. Authors will have the opportunity to submit extended versions of the papers published at the symposium in a special issue of a journal. For general information, contact the General co-Chairs. For paper submission information, contact the Program co-Chairs.