Salvatore Pontarelli

CNIT Researcher

Salvatore Pontarelli received a master degree in electronic engineering at University of Bologna in 2000. In 2003 takes its PhD degree in Microelectronics and Telecommunications from the University of Rome Tor Vergata. Currently, he works as Researcher at CNIT (Italian National Inter-University Consortium for Telecommunications), in the research unit of University of Rome Tor Vergata. Dott. Pontarelli has worked for several years in the Defect and Fault Tolerance Group (DFTGroup) coordinated by Prof. Adelio Salsano. His research activities was focuses on fault tolerance, on-line testing and error correction codes.
From 2009 we started working on topics related to the hardware design of network devices participating in several EU funded projects. In 2011 he was recipient of a CISCO Research Award for the study on the combined use of Bloom filters and Ternary CAM.


  • E-mail: salvatore.pontarelli at
  • Landline telephone number: +39 067259 7811

Research interests

  • Hardware architectures for high-speed packet processing
  • Hash based structures (Bloom filters, hash tables, etc)
  • Hardware design of software defined network devices
  • Stateful programmable data planes.

Selected list of pubblications

  • S. Pontarelli, P. Reviriego, “Cuckoo Cache: A Technique to Improve Flow Monitoring Throughput”, IEEE Internet Computing 20 (4), 46-53, 2016
  • M. Mitzenmacher, P. Reviriego, S. Pontarelli, “OMASS: One Memory Access Set Separation”, IEEE Transactions on Knowledge and Data Engineering 28 (7), 1940-1943
  • M. Bonola, G. Bianchi, G. Picierro, S. Pontarelli, M. Monaci, “StreaMon: a data-plane programming abstraction for Software-defined Stream Monitoring”, IEEE Transactions on Dependable and Secure Computing
  • S. Pontarelli, M. Bonola, G. Bianchi, A. Capone, C. Cascone, “Stateful Openflow: Hardware Proof of Concept”, in Proc. of the 16th IEEE International Conference on High Performance Switching and Routing (HPSR), 2015.
  • S. Pontarelli, G. Bianchi, S. Teofili, “Traffic-Aware Design of a High-Speed FPGA Network Intrusion Detection System”, IEEE Transactions on Computers, 62 (11), 2322-2334
  • S. Pontarelli, C. Greco, E. Nobile, S. Teofili, G. Bianchi, “Exploiting Dynamic Reconfiguration for FPGA based Network Intrusion Detection Systems”, Field Programmable Logic and Applications (FPL), 2010
  • C. Greco, E. Nobile, S. Pontarelli, S. Teofili, “An FPGA based architecture for complex rule matching with stateful inspection of multiple TCP connections”, Programmable Logic Conference (SPL), 2010

This is a partial and non updated list of papers. An almost complete and automatically updated publication list is available at Google Scholar Citations